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Chapter 1: What’s New in ISE Design Suite
Additional IP supporting AXI4 Interfaces
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The latest versions of CORE Generator IP have been updated with Production AXI4
interface support. For more detailed support information see
www.xilinx.com/ipcenter/axi4_ip.htm .
In general, the AXI4 interface will be supported by the latest version of an IP, for
Virtex?-7, Kintex?-7, Virtex?-6 and Spartan?-6 device families. Older "Production"
versions of IP will continue to support the legacy interface for the respective core on
Virtex?-6, Spartan?-6, Virtex?-5, Virtex?-4 and Spartan?-3 device families only.
For general information on Xilinx AXI4 support see
www.xilinx.com/ipcenter/axi4.htm .
A comprehensive listing of cores that have been updated in this release can be viewed
at www.xilinx.com/ipcenter/coregen/updates_13_1.htm .
CORE Generator Enhancements
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Introducing support for IP-XACT based IP repositories for Xilinx and Alliance
Program Member IP. (Requires no changes to existing CORE Generator, PlanAhead
and Project Navigator user flows.)
Addition of “Manage IP” pull-down menu to provide repository and IP management
features.
Display of AXI4 support by each IP in the IP catalog has been expanded to display the
various AXI4 interfaces in separate sortable columns: AXI4, AXI4-Stream and AXI4-
Lite
Individual ports in IP symbols can now be grouped into AXI4 channels for simplified
symbol views.
PlanAhead IP Design Flow Enhancements
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Introducing support for IP-XACT based IP repositories for Xilinx and Alliance
Program Member IP (Requires no changes to the existing PlanAhead software IP
flow).
Display of AXI4 support by each IP in the IP catalog has been expanded to display the
various AXI4 interfaces in separate sortable columns: AXI4, AXI4-Stream, and AXI4-
Lite.
Support added for Automatic IP Upgrade flow.
Important Release Information
General
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Pinouts on Kintex-7 and Virtex-7 devices are subject to change because package files
are not yet finalized for these families. Pinout changes may require design re-
implementation in a future Xilinx software release.
Default IO standards for Kintex-7 and Virtex-7 devices will change in a future Xilinx
software release.
Changes will be made to XC7V1500T and XC7V2000T device models in a future Xilinx
software release. 13.1 implementation design files (.NCD) targeting these devices will
be invalidated at that time, and designs will need to be re-implemented.
24
www.xilinx.com
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
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